This little tutorial is supposed to be dynamically updated when I feel that more info is needed or find errors in it.
VCS is a simulator from Synopsys which is known to be far superior to Xilinx ISim. It support multiple languajes such as the most popular Verilog, VHDL, SystemVerilog.
The general workflow when simulating with VCS consist of the following steps.
- vhdlan: The compiler for VHDL files
- vlogan: The compiler for Verilog and SystemVerilog files.
VHDL uses libraries to organize code, getting vhdlan to compile them is not straight forward since vcs needs to map them to some directory and then link them.
To achieve this you must create a directory with the name of each the library in your pwd to be able to map the libraries to a physical directory. The way to tell vcs how to map each library to the directories a special file is needed: .synopsys_vss.setup. This file can be on your VCS instalation path, in your $HOME or in your pwd, vhdlan will look for the file in this particular order.
The syntax of this file is somehow easy, you first need to map the WORK library to a name, which then must be maped to a physical directory, after that, each library must be mapped to a physical directory on each line.
In the following example, there are two libraries, MY_LIB with some modules of my own and UTIL_LIB which have util modules designed over the time.
WORK > DEFAULTThis is a simple command line used to compile VHDL files with libraries
DEFAULT : ./work
MY_LIB : ./MY_LIB
UTIL_LIB : ./UTIL_LIB
vhdlan -work <library_dir> -f <filename_of_file_list>
Verilog doesn't uses libraries so there is not need to do tricks with the libraries. Still it's useful to know some tricks about this complier.
vlogan have some useful flags that helps to structure the code and maintain isolated the simulation environment to the development one.
- +incdir+: Specify the path where vlogan will look for the files to compile.
- +define+: Define a text macro at compile time.
- +v2k: Enables the use of Verilog Standard 2001
- -svlog or -sverilog: Enables the analysis of SystemVerilog code.
This is the simple command line used to compile Verilog files using 2001 standard and a SystemVerilog test bench.
vlogan +v2k +incdirvlogan write it's output in a directory AN.DB which can be deleted in a cleanup process to keep workspace clean.
vlogan +v2k -sverilog +incdir
Once every file needed in a design is compiled, now it is time to elaborate the executable binary. The command to elaborate is vcs which take as parameter the top module to be simulated, usually the top module of the testbench.
The command to elaborate is:
vcs -debug_allwhere the flag -debug_all tell the tool to enable the simulation GUI and the necessary debug information to add breakpoints and line stepping. The glbl argument is needed to use Xilinx components.
The elaboration command generates an executable file with the name of simv which must be executed to start the simulation. The default behavior of this executable is to run and output messages from the test bench to stdout. Normally what is needed is to get a GUI where to see the waves and analyze the signal values at each time, this is done with the -gui parameter.
The command to execute the simulation with a GUI is:
This is the basic workflow needed to simulate a design in VCS, each of the tools have a lot more parameters that can be used to get specialized behavior when needed. All of them come with the documentation of the tools through the manuals or the -h parameter.
 VCS and coverage by Aviral Mittal
Update: This is the original link to the article I found useful
Update: Fix some escaped out <info> comments.